The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for manufacturing a photolithography mask with electroforming technique. Merely by way of example, the invention has been applied to one or more masks for the manufacture of integrated circuits. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is the ability to procure mask sets that provide high pattern fidelity and high device reliability.
Fabrication of custom integrated circuits using chip foundry services has evolved over the years. Fabless chip companies often design the custom integrated circuits. Such custom integrated circuits require a set of custom masks commonly called “reticles” to be manufactured. A chip foundry company called Semiconductor Manufacturing International Corporation (SMIC) of Shanghai, China is an example of a chip company that performs foundry services. Although fabless chip companies and foundry services have increased through the years, many limitations still exist. For example, mask sets used for the manufacture of the custom integrated circuits can usually provide only limited pattern fidelity and device reliability. If a mask set provides a metal-line pattern that is narrower than the design specification, the fabricated metal line may be over-etched and create an undesirable open circuit. These and other limitations are described throughout the present specification and more particularly below.
FIGS. 1-7 are simplified diagrams for a conventional method of making a photolithography mask. The method includes process 110 for quartz layer formation, process 120 for chromium layer formation, process 130 for anti-reflection layer formation, process 140 for photoresist layer formation, process 150 for photoresist layer exposure, process 160 for photoresist layer development, and process 170 for chromium layer etching and photoresist layer stripping. At process 110 for quartz layer formation, quartz layer 112 is fabricated. At process 120 for chromium layer formation, chromium layer 122 is deposited by sputtering on quartz layer 112. At process 130 for anti-reflection layer formation, anti-reflection layer 132 is deposited by sputtering on chromium layer 122. For example, anti-reflection layer 132 is composed of chromium oxide. At process 140 for photoresist layer formation, photoresist layer 142 is coated onto anti-reflection layer 132. For example, photoresist layer 142 is composed of positive photoresist. Positive photoresist usually includes large molecules. Upon exposure, the large molecules can be converted into small molecules, and small molecules can usually dissolve fast in certain chemical solutions. At process 160 for photoresist development, portions of photoresist layer 142 are removed, and remaining portions of photoresist layer 142 subsequently form photoresist pattern 162. As shown in FIG. 6, photoresist pattern 162 includes photoresist sub-layers 164. At process 170 for chromium layer etching and photoresist layer stripping, portions of anti-reflection layer 132 are removed, and remaining portions of anti-reflection layer 132 form anti-reflection pattern 172. Anti-reflection pattern 172 includes anti-reflection sub-layers 174. Etching anti-reflection layer 132 may use a dry etching process, a wet etching process, or a combination thereof. Similarly, portions of chromium layer 122 are removed, and remaining portions of chromium layer 122 form chromium pattern 176. Chromium pattern 176 includes chromium sub-layers 178. Etching chromium layer 122 may use a dry etching process, a wet etching process, or a combination thereof. With formation of anti-reflection pattern 172 and formation of chromium pattern 176, photoresist pattern 162 is removed. Consequently, quartz layer 112, chromium pattern 176 and anti-reflection pattern 172 form photolithography mask 179. Quartz layer 112 usually provides high transparency for light source used to pattern photoresist layers when photolithography mask 179 is being used.
During the fabrication of photolithography mask 179, photoresist sub-layers 164 may have widths 166 that vary with different sub-layers and differ from desired specifications as shown in FIG. 6. For example, width 166 may be narrower than the desired specification. Consequently, anti-reflection sub-layers 174 and chromium sub-layers 178 may be narrower than the desired specifications as shown in FIG. 7. Thus, metal lines patterned by photolithography mask 179 may have widths narrower than the desired specifications. When the desired specifications shrink to a small feature size, for example 0.13 μm, the fabricated metal lines may contain broken segments and thus create undesirable open circuits. The open circuits decrease yield for semiconductor manufacturing and degrades reliability of semiconductor devices.
Hence, an improved technique for processing semiconductor devices is desired.